VME Fifo modules for the OD-DAQ:
C.A.E.N. V533
Pipeline FIFO buffer unit 256 x 32 bits (expandable to 4096 x 32 bits)
Documentation links:
-
C.A.E.N. model V533 product description and data sheet
- Fifo-loop subroutine flow charts for the Anti-Collector software
(by J.George):
- This document:
Table of data and flag input usage and VME
addresses
This is the current setup of the Fifo input channels at the OD-DAQ since
the upgrade to version 2 [8/1/96]:
| Fifo # | VME slot | base address | trigger
input | data input bits | data / flag name |
|---|
| 0 | slot 5 | 0xF10000 |
G + B (*) | 0...31 | Local Time |
|---|
| 1 | slot 8 |
0xF00000 | G + B
(*) | 0...15 | Event Number |
|---|
| 16 | global trigger (long) (*3) |
| 17 | End-of-BIP flag |
| 18 | GPS fine-tune flag (*4) |
| 19 | global trigger (40 nsec) flag |
| 20...23 | BIP hut 1...4 (inverted) |
| 24 | AUX bit (*4) |
| 25 | Veto flag (inverted) |
| 26 | Reset Veto flag (inverted) |
| 27...31 | -- free / not used yet -- |
| 2 | slot 6 | 0xF20000 | G + B
(*) | 0...31 | Local Time (*2) |
|---|
- where:
- (*)
- = Global Triggers combined (OR) with End-of-BIP Triggers.
- (*2)
- = In the future, this will be dedicated to time-stamp the
End-of-BIP Triggers only, in order to measure the TDC
deadtimes. Currently, this fifo is only used for backup of
Fifo 0.
- (*3)
- = This is the original trigger signal from the Event Number
cable (17th bit), as originated from the EVENT COUNT
DRIVER box. It's of approx. 250...350 nsec length.
- (*4)
- = Not implemented or used yet with the current OD-DAQ version.
Modifications on the V533 modules for the SuperK OD-DAQ
Note: Two modifications had to be done
with the original C.A.E.N. V533
boards before they could be implemented into the OD-DAQ system!
- Each Fifo module was delivered by C.A.E.N. with a CERN-specific
"Paux" connector, an additional special 30-pin DIN connector
for the VMEbus backplane in order to supply the board with -5.2V for
the ECL and NIM circuits. Standard VME crates on the US market were
not equipped with the counter parts nor an additional -5.2V power supply,
and the European versions we found were far more expensive than the
standard crates. Instead, we found a simple solution by removing
the Paux connector and replacing it with a $1 voltage regulator
IC (type 7905) to derive the needed -5.2V (-5V) from the -12V
standard supply voltage. See photo below for the position of the
regulator on the board.
- The termination resistors R1 and R4 - both 51 Ohms - for the NIM inputs
TRIG and REFCLK had to be removed in order to allow
hooking up the trigger/clock signals in a serial chain.
The appropiate termination is then done with an external Lemo
50-Ohm Terminator.
How to expand the fifo buffer depth
With the original manufacturer setup, the V533 module consists of two
256 x 32-bit fifo buffers. The first one is a continuously running
circular buffer, latching 32-bit input data with each new REFCLK pulse
(50 MHz). The second buffer then reads 3-15 words (programmable amount)
from the first buffer with a programmable shift of 0-255 clock ticks
at each TRIG pulse. In other words, the first buffer acts as a programmable
delay and the second buffer is an "event buffer".
For the OD-DAQ the event buffer latches three 32-bit words at each trigger.
Thus, with a fifo depth of 256 words, we can save up to 85 trigger events
(*) without reading it out through the VMEbus.
If more than 85 events occur between VME readouts then the module sets a
BUSY flag, telling the user that the buffer is full and more events
are ignored from now on.
In order to keep up with higher trigger rates and trigger bursts at SuperK
we soon have to expand the fifo depth of the event buffer. These are the
positions U26...U29 (replace IDT72201 with IDT72241) and
position U33 (replace IDT7201 with IDT7204). Latter IC
is used as an internal event count register buffer of the V533 module.
With the new ICs the event buffer is then 4096 x 32-bit wide, allowing us 16
times as many events - 1365 instead of 85 (*) - to
pile up before a BUSY state occurs again!
- (*)
- actually, in the current OD-DAQ
hardware the Fifo Trigger inputs are fed with an OR of the Global
Triggers and the "End-of-BIP" triggers. Latter ones occur
each time at the end of a TDC busy period and are used to measure
the deadtimes of the Fastbus modules. In average, almost every
Global trigger is followed by a End-of-BIP trigger a couple of
microseconds later. Thus, a fifo buffer of 85 events means in
average a maximum of only 42 Global Trigger events can be allowed
between consecutive VMEbus readouts.
Dito for expanding the buffer to 4k words means, we'll then have
a Global Trigger buffer capacity of approx. 682 - which is still
16 times more than before ...
last edited 3/31/97 [HGB]
