Fanin/out and Calibration Module (FCM)

OD DAQ Version 2

This custom board is part of the SuperK OD DAQ system as installed during the custom electronics upgrade from version 1 to version 2 at August 01, 1996. The ENT board sits in slot 12 of the OD VME crate in the central hut.

Overview of this document

Functions
Inputs and Outputs
Jumpers
LEDs and their Functions
Schematics and PCB Layout
PLD Source Codes
Performance Test Results
Revision Notes

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Functions

Fanout of trigger and TDC test/calibration signals to the Fastbus Interface Modules in the outer huts, via the "CAL" cables.
Fanin of manual test trigger pulses activated from the test pushbuttons of the Fastbus Interface Modules in the outer huts. The logic OR-ed result of these inputs is then provided for further distribution through the Event Number Translator module.
VME-programmable 16-bit digital test pattern.
up to 3 VME-programmable auxiliary outputs.

Block diagram (also as postscript available):

Inputs and Outputs

Name I/O Level Where Function

TRG input NIM Lemo Global trigger from the TRG fanout of the Eventnumber translator board. This signal is then fanned out to the Fastbus Interface modules in the outer huts where it will be used for TDC event number "chopping" since the TDCs can only record pulse transitions in the data but no static signals.

Fast FSCC Reset (*) input NIM LEMO Input for a programmable pulse of 1-2 second width for the "Fast Reset method" which is then fanned out to the Fastbus Interface modules in the outer huts, from where it will go to the input ports of the FSCCs. Usually this input is connected via a short LEMO cable with the AUX-1 output which will provide a VME-programmed pulse for this purpose. For test purposes, a signal/pulse generator can be connected instead.

TDC Start input NIM Lemo Input for "TDC Common Start" pulses which are then fanned out to the Fastbus Interface modules and from there to the TR3 line of the Fastbus backplane (i.e. invoke "Common Start" with the TDCs).

Test TRG output TTL LEMO Combined (logic OR) test trigger pulses coming from the FB modules in the outer huts via the "CAL" cables.

"CAL" cable I/O's 4*RS485 four 8-pin Modular Calibration and Test signals from and to the FIV modules in the four outer huts. One modular connector for each hut. Pin assignments:

1/2 = RS485 output = +/- FSCC Fast Reset pulse (or TDC Clear)
3/6 = RS485 input = +/- Manual Test Trigger
4/5 = RS485 output = +/- Global Trigger (T0 Reference for TDCs)
7/8 = RS485 output = +/- TDC Common Start

AUX-1 output TTL or NIM Lemo VME-programmable output. See the PLD source code for the address [Default = hex.D600, data bit 0]. The signal level can be set via jumper JP6 to either TTL or NIM standard.
With the current OD DAQ setup (as of Sep. 1996) this output is reserved for the Fast FSCC Reset activation signal, connected to the Fast FSCC Reset input with a short Lemo cable.

AUX-2 output TTL or NIM Lemo same as AUX-1, except VME data bit 1 is used instead of bit 0.
Unused with the current OD DAQ setup (as of Sep. 1996)

BIP-OR (**) input TTL Lemo For the combined BIP (Busy-In-Progress) signal from the TDCs delivered by the VFI board.

Test pattern outputs d-ECL 34-pin header 16-bit test pattern, programmable via the VMEbus. For the VME address see the PLD source code [Default = hex.D000].

pin 1/2 = +/- test bit 0
pin 3/4 = +/- test bit 1
:
pin 31/32 = +/- test bit 15
pin 33/34 = not used

Changes from original version of this board (see revision notes):

(*)
formerly TDC clear input
(**)
formerly AUX-3 output

Inputs and Outputs
Name	I/O	Level	Where	Function
TRG	input	NIM	Lemo	Global trigger from the TRG fanout of the Eventnumber translator board. This signal is then fanned out to the Fastbus Interface modules in the outer huts where it will be used for TDC event number "chopping" since the TDCs can only record pulse transitions in the data but no static signals.
Fast FSCC Reset ()*	input	NIM	LEMO	Input for a programmable pulse of 1-2 second width for the "Fast Reset method" which is then fanned out to the Fastbus Interface modules in the outer huts, from where it will go to the input ports of the FSCCs. Usually this input is connected via a short LEMO cable with the AUX-1 output which will provide a VME-programmed pulse for this purpose. For test purposes, a signal/pulse generator can be connected instead.
TDC Start	input	NIM	Lemo	Input for "TDC Common Start" pulses which are then fanned out to the Fastbus Interface modules and from there to the TR3 line of the Fastbus backplane (i.e. invoke "Common Start" with the TDCs).
Test TRG	output	TTL	LEMO	Combined (logic OR) test trigger pulses coming from the FB modules in the outer huts via the "CAL" cables.
"CAL" cable	I/O's	4*RS485	four 8-pin Modular	Calibration and Test signals from and to the FIV modules in the four outer huts. One modular connector for each hut. Pin assignments: 1/2 = RS485 output = +/- FSCC Fast Reset pulse (or TDC Clear) 3/6 = RS485 input = +/- Manual Test Trigger 4/5 = RS485 output = +/- Global Trigger (T0 Reference for TDCs) 7/8 = RS485 output = +/- TDC Common Start
AUX-1	output	TTL or NIM	Lemo	VME-programmable output. See the PLD source code for the address [Default = hex.D600, data bit 0]. The signal level can be set via jumper JP6 to either TTL or NIM standard. With the current OD DAQ setup (as of Sep. 1996) this output is reserved for the Fast FSCC Reset activation signal, connected to the Fast FSCC Reset input* with a short Lemo cable.*
AUX-2	output	TTL or NIM	Lemo	same as AUX-1, except VME data bit 1 is used instead of bit 0. Unused with the current OD DAQ setup (as of Sep. 1996)
BIP-OR ()	input	TTL	Lemo	For the combined BIP (Busy-In-Progress) signal from the TDCs delivered by the VFI board.
Test pattern	outputs	d-ECL	34-pin header	16-bit test pattern, programmable via the VMEbus. For the VME address see the PLD source code [Default = hex.D000]. pin 1/2 = +/- test bit 0 pin 3/4 = +/- test bit 1 : pin 31/32 = +/- test bit 15 pin 33/34 = not used
Changes from original version of this board (see revision notes): () formerly TDC clear* input () formerly AUX-3** output

Jumpers

See also the board layout sketch (postscript) for the locations on the board:

JP6:: Select TTL or NIM signal level for the AUX-1 output. [Default = NIM]
JP7:: Select TTL or NIM signal level for the AUX-2 output. [Default = NIM]
JP8:: Not used since rev. version 2.3, since AUX-3 is disabled now.

LEDs and their functions

From top to bottom:

Global Trigger (green): Sits next to the Global Trigger input connector. It should flash briefly for each new trigger pulse. If it doesn't flash, please check if the Lemo cable is correctly hooked up or if the 51 Ohm termination resistor sits in the R4 socket.
Fast FSCC Reset Input (red) status display.
TDC Start Input (orange) status display.
Remote Test Triggers 1-4 (yellow): Indicate whether the test trigger pushbutton of one of the Fastbus Interface modules in the outer huts has been pushed. One LED for each outer hut.
AUX signal 1 (green) status display.
AUX signal 2 (green) status display.
BIP-OR (green) status display.
16-bit Test Pattern (yellow): status display of the VME-programmable digital pattern; one LED for each of the 16 bits.
VME Acknowledge (orange): Indicates when the VMEbus is accessing this module or the VFI module, i.e. when write commands to their address ranges have been activated. See the PLD code for the actual addresses [Default = D000...D7FF (hex.)].

Schematics and PCB Layout

The schematics were edited with ORCAD STD V4 on a 486 PC:

page 1 (gif or postscript): root page + "CAL" signals fanin/out.
page 2 (gif or postscript): VME supply and address decoder.
page 3 (gif or postscript): 16-bit pattern and AUX drivers.

The 2-layer PCB layout was edited with TANGO PCB V2, also on a 486 PC. Here's the gif or postscript file of the silk print layer.

PLD source codes

One PLD chip is used on this board for VME address decoding: Position U15 (type P22V10). The source code (FCM.TDL) is written for TANGO PLD for compilation to standard JEDEC format.

The current setup of this address decoder is:

Addr.	Data bits	Addr. Modif.	Write	Addr. Sel.	action
A0...15	active	AM0...5	/WR	/AS	action
0xD000	D0...15	0x29	0	0	set new 16-bit test pattern for front panel access
0xD600	D0...2	0x29	0	0	set AUX ouputs (D0...2=AUX1...3)
X	X	X	1	X	(no action)
X	X	X	X	1	(no action)

where X = don't care

Performance Test Results

The following pictures were taken during measurements with digital scopes at the inputs and outputs of the FCM board. Some of the tests were done with the real system at the SuperK site. The measurements were either performed with a 2-channel LeCroy scope with 2.5 GSamples/channel or a 4-channel Tektronix scope with 1 GSamples/channel.

Revison Notes

06/21/96 - Version 2.0: FCM design finalized for etching.
07/13/96 - Version 2.1:
- Minor mistake in final layout design caused the NIM-level signals of all 3 AUX outputs to be inverted. Solution: cross the rectifier pairs D10/D11, D15/D16, D18/D19 with each other, e.g. such that the anode of D10 goes into the original node for anode of D11 and vice versa.
- Add sockets for removable 50 Ohm NIM terminator resistors on R4 (TRG input), R2 (TDC Clear input) and R6 (TDC Start input). See also the layout sketch (postscript) for their positions.
08/05/96 - Version 2.1a:
- Rectifiers added in the LED display circuitry for the TDC Clear and TDC Start signals, such that the according LED from now on will display long pulses correctly and not just briefly flash for ~50 msec.
- The input TDC Clear is renamed to Fast FSCC Reset. No change in circuitry functions though.
09/05/96 - Version 2.2:
- The former AUX-3 output is now re-assigned to BIP-OR input.
- TRG veto circuit (BIP veto) implemented. This might avoid further confusion of recorded trigger reference pulses at the TDCs during their busy (BIP) phases - where they shouldn't register any data at all according to the LeCroy manual, but appearantly did occasionally as observed by the during extended data taking runs.

rev. HGB 01/27/97. Any comments to berns@phys.washington.edu are welcome!