Fastbus Interface to VME (FIV) board

for the OD DAQ Version 2

Overview of this document

• Functions
• Inputs and Outputs
• Jumpers, Switches and Trimpots
• LEDs and their Functions
• Schematics and PCB Layout
• PLD Source Codes
• Performance Test Results
• Revision Notes

Note: This site is best viewed with Netscape Ver.2 or compatible !

• Interface between the Fastbus electronics in the outer huts and the VME electronics in the center hut. Due to the long distances between the units in the different electronics huts, the control and calibration signals are sent through long twisted-pair cables with differential signals (RS485/422 or dECL) which then are converted on either side of the cables to the appropiate signal levels needed for the specific functions (TTL, ECL, etc.):
  • Control signals via the "BIP" cable from/to the VFI card:
    • Struck Latch Stop Trigger (STRG).
    • TDC Common Stop Trigger (FTRG) to TR6 Fastbus backplane pin.
    • FSCC Remote Reset signal.
    • TDC Busy-In-Progress (BIP) from TR7 Fastbus backplane pin.
  • Test and TDC calibration signals via the "CAL" cable from/to the FCM card:
    • Global Trigger for event number "chopping".
    • TDC Common Start Pulse to TR3 Fastbus backplane pin.
    • FSCC Fast Reset / TDC Clear.
    • Manual Test Trigger return.
• Generates a 200 nsec trigger strobe (TSTRB) pulse for the FSCC at each trailing edge of a TDC BIP pulse.
• Pushbutton for generating manual single test triggers.
• Transceiver for the event number from the EVENT COUNT DRIVER to the data input of the Struck latch.
• Event number "chopping" and Global Trigger Reference driver for the free TDC data channels.
• Monitor for the Fastbus power supply voltages with a warning beeper and flashing LEDs in case of malfunction.

Inputs and Outputs
Name	I/O	level	where	function
Event Number	inputs	17*dECL	40-pin header	Receives the 16-bit event number and optional trigger (if selected) from the EVENT COUNT DRIVER box. Pin assignments: 1/2 = (not used) 3/4 = +/- event number bit 0 5/6 = +/- event number bit 1 -:- = +/- event number bit : 33/34 = +/- event number bit 15 35/36 = +/- optional trigger signal 37...40 = (not used)
Event Number	outputs	16*dECL	34-pin header	16-bit driver output for the Struck latch data input. Pin assignments: 1/2 = +/- event number bit 0 3/4 = +/- event number bit 1 -:- = +/- event number bit : 31/32 = +/- event number bit 15 33/34 = (not used)
Chopped Event Number	outputs	17*dECL	34-pin header	17-bit "chopped" event number and reference global trigger (T0) driver output for the free channels of TDC data inputs. Pin assignments: 1/2 = +/- output bit 0 3/4 = +/- output bit 1 -:- = +/- output bit : 31/32 = +/- output bit 15 33/34 = +/- output bit 16 (optional)
Struck Stop (STRG)	output	dECL	10-pin header	Driver output for the Struck latch Control Input Port 1. Pin assignments: 1/2 = +/- STRG signal other = (not used)
BIP cable	I/O's	3*RS485 + 1*dECL	8-pin Modular	Control signals from and to the VFI module in the center hut VME crate. Pin assignments: 1/2 = dECL input = +/- Struck Stop Trigger (STRG) 3/6 = RS485 input = +/- TDC Common Stop Trigger (FTRG) 4/5 = RS485 input = +/- FSCC Reset pulse 7/8 = RS485 output = +/- TDC BIP signal
CAL cable	I/O's	4*RS485	8-pin Modular	Calibration and Test signals from and to the FCM module in the center hut VME crate. Pin assignments: 1/2 = RS485 input = +/- FSCC Fast Reset pulse (or TDC Clear) 3/6 = RS485 output = +/- Manual Test Trigger 4/5 = RS485 input = +/- Global Trigger (T0 Reference for TDCs) 7/8 = RS485 input = +/- TDC Common Start
FSCC Reset	output	TTL	Lemo	VME-programmable FSCC (full, "slow") Reset signal. Connects to the Reset input near the Reset pushbutton on the FSCC front panel with a short Lemo coax cable.
FSCC TSTRB	output	NIM	Lemo	200 nsec pulse at the trailing edge of each TDC BIP pulse tells the FSCC that data is ready to read. Connects to the TSTRB input on the FSCC front panel with a short Lemo coax cable.
Trigger (optional)	input	NIM	Lemo	Optional (test) trigger input for the event number chopper. [Default = disabled]
FSCC Fast Reset	output	Rs485	Dual Lemo	Fast, on-the-fly, reset trigger for the FSCC. Connects to the Input Port of the FSCC module via short twisted-pair cable.
TR0	output	ECL	Fastbus backplane	TDC Fast Clear signal, optional control from the VME in the center hut via the "CAL" cable. [Default = disabled, jumper JP9 open]
TR3	output	ECL	Fastbus backplane	TDC Common Start signal, optional control or calibration from the VME in the center hut via the "CAL" cable. [Default = disabled, jumper JP10 open]
TR6	output	ECL	Fastbus backplane	TDC Common Stop (FTRG) signal, transceived from the VME in the center hut via the "BIP" cable. [Default = enabled, jumper JP11 closed]
TR7	input	ECL	Fastbus backplane	TDC BIP signal.

JP1:

(labeled "INV") choice of inverting or keeping the event number bits as is before going thru the "chopper" section:

• open: invert the event numbers
• closed: don't invert the event numbers [DEFAULT]

JP2:

(labeled "EDGE") choice of using both edges (leading and trailing) or just the leading edge of the trigger signal for the event number "chopping" method:

• open: use trigger's leading edge only (flip-flop method) [DEFAULT]
• closed: use both trigger edges (logical AND method)

JP6:

Select Trigger Source for the "event number chopper" section, by placing a jumper at one of the following pin position choices:

• 1/2 = from event number cable
• 3/4 = from "BIP" cable [DEFAULT]
• 5/6 = from Lemo (NIM) input

JP9:

Enable TR0 = TDC Clear.

• open: disable [DEFAULT]
• closed: enable

JP10:

Enable TR3 = TDC Common Start.

• open: disable [DEFAULT]
• closed: enable

JP11:

Enable TR6 = TDC Common Stop.

• open: disable
• closed: enable [DEFAULT]

JP13:

Enable Local Test Trigger: With the default setup of the OD DAQ system, a global test trigger will be generated each time the test pusbutton of the FIV board in one of the 4 outer huts has been activated. Optionally, the global test triggering can be disabled within the center hut VME crate and localized for each outer hut by setting this jumper (JP13).

• open: disable [DEFAULT]
• closed: enable

JP14:

[ Not used anymore, keep open !! ]

R98:

Adjust upper threshold ("+REF") of the Fastbus voltage supply monitor from 0V (=-100%) to 5V (=+150%). Use a voltmeter at testpoint TP1. [DEFAULT = +5% = 2.05V]

R99:

Adjust lower threshold ("-REF") of the Fastbus voltage supply monitor from 0V (=-100%) to 5V (=+150%). Use a voltmeter at testpoint TP3. [DEFAULT = -10% = 1.90V].

S1/2:

16 DIP switches (2*8) for "event number chopper" output select. Each of the switches has the following choices:

• open (OFF): output bit = chopped event number bit
• closed (ON): output bit = trigger (T0) signal

[Default: positions 1...4 of S1 are open, all others closed; i.e. bits 0-3 are event number bits, the others triggers (for T0 reference at the TDC)]

S3:

Manual Test Trigger Pushbutton. Starts a test trigger either remotely through activating a global test trigger in the central hut's VME crate or locally for the single Fastbus crate (see jumper JP13 description).

1. Power good (blue): If this LED is on and the red LED below is completely off, then the Fastbus power supply is working perfectly within its margin. All five voltages are ok!
2. Power bad (red): This LED will flash approx. twice per second when any of the Fastbus supply voltages isnot operating correctly. Along with the flashing LED you will hear a warning beeper as well.
3. TR0 (Clear) (red): Status of the TR0 line (= TDC Fast Clear) on the Fastbus backplane. Currently, this function is not used with the OD DAQ setup.
4. TR3 (Start) (yellow): Status of the TR3 line (= TDC Common Start) on the Fastbus backplane. The Common Start option will only be used during OD DAQ (calibration) tests, and not during regular runs.
5. TR6 (Stop) (green): Status of the TR6 line (= TDC Common Stop) on the Fastbus backplane. Each time when a Common Stop Trigger is sent from within the VME elctronics of the center hut, you will see this LED briefly flashing.
6. TR7 (BIP) (orange): Status of the TR7 line (= TDC Busy-In-Progress) on the Fastbus backplane. Indicates whenever the TDCs are busy and not ready (yet) for new data.
7. Event Number bits (16x yellow): Display of the 16-bit event number status. The top LED inducates the MSB, and the bottom one the LSB.
8. Struck Stop Trigger (yellow): Sits next to the 10-pin header for the Stop Trigger cable to the Struck Latch. It should flash briefly each time when new triggers are processed.
9. Manual Test Trigger (green): Sits next to the Manual Test Trigger pushbutton. It'll flash each time the pushbutton is activated. The button itself can only be reached with a pointy object such as a small screw driver, etc. (when a front panel is mounted). This is for safety reasons, because:
   Note: NO test trigger should be generated during a normal run!!
10. FSCC Full Reset (red): Indicates when a remote FSCC reset command has been sent from within the center hut. Along with the LED flashing you will hear a short high-pitched sound from the warning beeper.
11. FSCC TSTRB (yellow): At the trailing edge of each TDC BIP signal, a 200 nsec Strobe signal is sent to the FSCC to inform of new data to be processed. Thus, this LED should flash each time when you see the TR7 (BIP) LED flashing.
12. External Trigger (green): Sits next to the Ext. Trigger input connector, and is only used for test purposes.
13. FSCC Fast Reset (orange): Indicates when a fast FSCC Reset command has been issued from within the center hut.

• page 1: (gif or postscript) root page, eventnumber interface and "chopper",
• page 2: (gif or postscript) Fastbus backplane and I/O section,
• page 3: (gif or postscript) Fastbus supply and TR lines monitor.

• 06/21/96 - Version 2.0: FIV design finalized for etching.

• 07/14/96 - Version 2.1:
  • Sockets added for removable 50 Ohm resistors (NIM terminators) at R60, near the "Trigger (optional)" input connector.
  • Changed R73 to 2.2kOhms and C32 to 4.7nF to change the Test Trigger delay to the TDC common stop section from 16 µsec to 8 µsec.
  • Inverted the Test Trigger signal at the "CAL" cable by swapping the U22B input (pin3) connection at U30A from pin 13 to pin 4.

• 07/29/96 - Version 2.2:
  • Inverted the Struck Stop (STRG) output by swapping the differential ouput pins of U16B (pins 1 and 3) which are connected to the JP7 header (pins 1 and 2).

• 08/05/96 - Version 2.2A:
  • Added link for "Fast FSCC Reset" method, by joining the differential CLEAR lines (U25A pins 7 and 8 or "CAL" connector JP12 pins 1 and 2) with the former diff. VETO lines (U28B pins 5 and 6 or J4 signal pins). R77 was then removed.