VME-Fastbus Interface (VFI) Board

OD DAQ Version 2

This custom board is part of the SuperK OD DAQ system as installed during the custom electronics upgrade from version 1 to version 2 at August 01, 1996. The VFI board sits in slot 7 of the OD VME crate in the central hut.

Overview of this document

Functions
Inputs and Outputs
Jumpers and DIP Switches
LEDs and their Functions
Schematics and PCB Layout
PLD Source Codes
Performance Test Results
Revision Notes

Note: This site is best viewed with Netscape Ver.2 or compatible !

Functions

This module is the main trigger interface between the VME electronics in the center hut and the Fastbus electronics in the outer huts. The following trigger and control signals are transmitted to/from the Fastbus Interface modules in the outer huts via LAN-type twisted-pair cables, called "BIP" cables:

Common Stop Trigger for the TDCs,
Common Clock (Stop Trigger) for the Struck latches,
Remote FSCC Reset for VME-commandable reset of the FSCC controllers,
Busy-In-Progress (BIP) signals from the TDCs.

Other functions are:

Digital delay of global triggers before transmitting them to the TDCs as Common Stop Triggers. Programmable via dip switches in 20nsec steps from 0 to 19.5µsec.
Vetoing of TDC Common Stop Triggers and Struck latch Stop Triggers if
- at least one of the TDCs is busy, i.e. any of the BIP signals is logic high, or
- the digital delay circuit is busy, i.e. after the global trigger (which started the delay sequence) until a BIP signal returns from the outer huts, or
- VME veto command (from the collector software on sukant), or
- a manual veto signal from the front panel input (optional).
Transfer the BIP signals from the outer huts to one of the Fifo input ports.
Generate short Remote FSCC Reset pulse(s) thru VME command from the sukant software.
Driver for the LED Display Box.

Block Diagram (also as postscript file):

Inputs and Outputs

Name I/O level where function

TRG input NIM LEMO Global trigger via fanout of the ENT board.

Veto output TTL LEMO Monitor output of the Trigger Veto status. Used for debugging and testing only.

Fifo Busy input TTL LEMO Busy signal of one of the Fifo modules, just needed for the LED Display Box.

STRG output NIM LEMO Struck Stop Trigger monitor output, for debugging and test purposes only.

FTRG output NIM LEMO Fastbus Trigger (TDC Common Stop) monitor output, for debugging and test purposes only.

Test Veto input inv. TTL LEMO cable stud (Spare backup board only) External Veto input. A logic low TTL signal (e.g. a short or 50 Ohm terminator) at this input will set a veto condition for the STRG and FTRG pulse generator, i.e. global triggers will be vetoed until the signal changes to logic high TTL level.
[This connector stays unplugged during normal runs!]

"BIP" cables I/O's 3*RS485
+ 1*dECL four 8-pin Modular Control signals from and to the FIV modules in the four outer huts, one modular connector each. Pin assignments at each connector:
1/2 = dECL output = +/- Struck Stop Trigger (STRG)
3/6 = RS485 output = +/- TDC Common Stop Trigger (FTRG)
4/5 = RS485 output = +/- FSCC Reset pulse
7/8 = RS485 input = +/- TDC BIP signal

LED Box outputs TTL 16-pin header 7 signals for the LED Display Box on top of the VME crate. Pin configuration:
1 = Hut 4 TDCs Busy (=BIP4)
3 = Hut 3 TDCs Busy (=BIP3)
5 = Hut 2 TDCs Busy (=BIP2)
7 = Hut 1 TDCs Busy (=BIP1)
9 = Veto Flag
11 = Trigger OK
13 = Fifo VME Busy
15 = +5V (test)
even = Signal GND

Fifo Flags outputs RS485 14-pin header 7 flag signals for the second V533 Fifo module. Pin configuration:
1/2 = +/- Remote Veto Flag (VME programmed veto)
3/4 = +/- Veto Status Flag (combined Trigger Veto)
5/6 = +/- Auxiliary Flag (optional, fixed by jumper JP3 setting)
7/8 = +/- Hut 4 TDC Busy (=BIP4)
9/10 = +/- Hut 3 TDC Busy (=BIP3)
11/12 = +/- Hut 2 TDC Busy (=BIP2)
13/14 = +/- Hut 1 TDC Busy (=BIP1)

50MHz CLK input NIM LEMO Input for the 50 MHz clock signal (20 nsec) from the LTC, needed for the Trigger Veto and Delay circuits.

BIP TRG output NIM LEMO End-of-BIP trigger pulse for the third V533 Fifo, in oder to measure TDC dead times with separate Fifo modules.
[Note: this signal is not used with the current OD DAQ setup! But a combined Global trigger / BIP trigger signal is generated at the LTC module instead. Implementation of separate Global Trigger and BIP trigger fifo banks is scheduled for Winter/Spring 1997.]

Inputs and Outputs
Name	I/O	level	where	function
TRG	input	NIM	LEMO	Global trigger via fanout of the ENT board.
Veto	output	TTL	LEMO	Monitor output of the Trigger Veto status. Used for debugging and testing only.
Fifo Busy	input	TTL	LEMO	Busy signal of one of the Fifo modules, just needed for the LED Display Box.
STRG	output	NIM	LEMO	Struck Stop Trigger monitor output, for debugging and test purposes only.
FTRG	output	NIM	LEMO	Fastbus Trigger (TDC Common Stop) monitor output, for debugging and test purposes only.
Test Veto	input	inv. TTL	LEMO cable stud	(Spare backup board only) External Veto input. A logic low TTL signal (e.g. a short or 50 Ohm terminator) at this input will set a veto condition for the STRG and FTRG pulse generator, i.e. global triggers will be vetoed until the signal changes to logic high TTL level. [This connector stays unplugged during normal runs!]
"BIP" cables	I/O's	3RS485 + 1dECL	four 8-pin Modular	Control signals from and to the FIV modules in the four outer huts, one modular connector each. Pin assignments at each connector: 1/2 = dECL output = +/- Struck Stop Trigger (STRG) 3/6 = RS485 output = +/- TDC Common Stop Trigger (FTRG) 4/5 = RS485 output = +/- FSCC Reset pulse 7/8 = RS485 input = +/- TDC BIP signal
LED Box	outputs	TTL	16-pin header	7 signals for the LED Display Box on top of the VME crate. Pin configuration: 1 = Hut 4 TDCs Busy (=BIP4) 3 = Hut 3 TDCs Busy (=BIP3) 5 = Hut 2 TDCs Busy (=BIP2) 7 = Hut 1 TDCs Busy (=BIP1) 9 = Veto Flag 11 = Trigger OK 13 = Fifo VME Busy 15 = +5V (test) even = Signal GND
Fifo Flags	outputs	RS485	14-pin header	7 flag signals for the second V533 Fifo module. Pin configuration: 1/2 = +/- Remote Veto Flag (VME programmed veto) 3/4 = +/- Veto Status Flag (combined Trigger Veto) 5/6 = +/- Auxiliary Flag (optional, fixed by jumper JP3 setting) 7/8 = +/- Hut 4 TDC Busy (=BIP4) 9/10 = +/- Hut 3 TDC Busy (=BIP3) 11/12 = +/- Hut 2 TDC Busy (=BIP2) 13/14 = +/- Hut 1 TDC Busy (=BIP1)
50MHz CLK	input	NIM	LEMO	Input for the 50 MHz clock signal (20 nsec) from the LTC, needed for the Trigger Veto and Delay circuits.
BIP TRG	output	NIM	LEMO	End-of-BIP trigger pulse for the third V533 Fifo, in oder to measure TDC dead times with separate Fifo modules. [Note: this signal is not used with the current OD DAQ setup! But a combined Global trigger / BIP trigger signal is generated at the LTC module instead. Implementation of separate Global Trigger and BIP trigger fifo banks is scheduled for Winter/Spring 1997.]

Jumpers and DIP Switches

See also the board layout sketch (gif or postscript) for the locations.

JP3:

Set optional Auxiliary Flag Bit:

open = 1 / closed = 0

JP5:

Veto circuit setup

pins 1+2 (RVETO-EN):	open = enable VME programmable Reset Veto [DEFAULT] closed = disable Reset Veto
pins 3+4 (BIP-VETO):	open = enable BIP veto [DEFAULT] closed = disable BIP veto
pins 5+6 (BIP-LONG):	open = extend BIP veto for 200 nsec after end of BIP signal closed = keep BIP veto equal to length of BIP signal [DEFAULT]
pins 7+8 (BIP-INV):	open = BIP inputs are inverted closed = BIP inputs are non-inverted [DEFAULT]

S1:

10-position dip switch to set the Fastbus TDC Common Stop Trigger (FTRG) delay (versus the Global Trigger) in 20 nsec steps. Depending on the setting of the dip switch a 50 MHz counter (20 nsec) counter is started as soon as a (not yet vetoed) Global Trigger arrives. The counter starts from the dip switch's digital value and then counts down to zero. When it reaches the value 50 (= 1 µsec left until 0) a 100 nsec TDC Common Stop Trigger (FTRG) is generated. Also, as long as the counter value is non-zero, a "Counter Busy Veto" signal is set and OR-ed with the BIP veto and programmable VME veto to suppress further Global Triggers for generating Struck and TDC Triggers.

delay timing diagram

The formulas for the count busy and FTRG delay lengths are:

Counter busy lenght: dip-switch_value * 20 nsec

FTRG delay lenght: Counter_busy_lenght - 920 nsec (+/-10 nsec)

Table of examples:

switch position										switch value	counter busy	FTRG delay
1	2	3	4	5	6	7	8	9	10	switch value	counter busy	FTRG delay
0	0	0	0	0	0	0	0	0	0	0	0 (invalid)	(invalid)
1	0	0	0	0	0	0	0	0	0	1	20 nsec	(no pulse)
0	1	0	0	0	0	0	0	0	0	2	40 nsec	(no pulse)
:	:	:	:	:	:	:	:	:	:	:	:	:
1	0	0	0	1	1	0	0	0	0	49	980 nsec	(no pulse)
0	1	0	0	1	1	0	0	0	0	50	1.00 µsec	~80 nsec (min.)
:	:	:	:	:	:	:	:	:	:	:	:	:
1	0	0	0	0	1	1	0	0	0	97	1.94 µsec	1.00 µsec
1	1	0	0	1	0	0	1	0	0	147	2.94 µsec	2.00 µsec
1	1	1	0	1	1	1	1	0	0	247	4.94 µsec	4.00 µsec
1	1	0	1	1	0	1	0	1	0	347	6.94 µsec	6.00 µsec [DEFAULT]
1	1	1	1	1	1	0	1	1	0	447	8.94 µsec	8.00 µsec
1	1	0	0	1	0	0	0	0	1	547	10.94 µsec	10.00 µsec
1	1	1	0	0	0	0	1	0	1	647	12.94 µsec	12.00 µsec
1	1	0	1	0	1	1	1	0	1	747	14.94 µsec	14.00 µsec
1	1	1	1	0	0	1	0	1	1	847	16.94 µsec	16.00 µsec
1	1	0	0	1	1	0	1	1	1	947	18.94 µsec	18.00 µsec
0	1	1	1	1	1	1	1	1	1	1022	20.44 µsec	19.50 µsec (max.)
1	1	1	1	1	1	1	1	1	1	1023	0 (invalid)	(invalid)

where: 0=closed and 1=open

S2:

16-position rotary switch to set the Struck Stop Trigger (STRG) pulse width in 20nsec steps:

switch position	pulse width
0	no pulse
1	20 nsec
2	40 nsec
:	:
E	280 nsec
F	300 nsec [DEFAULT]

LEDs and their functions

Trigger (green) flashes briefly whenever a new Global Trigger arrives.
Veto (red): This LED is lit whenever any combination of the trigger veto conditions occurs, i.e. if
- any TDC in the outer huts is busy (BIP = high), or
- the TDC Common Stop (FTRG) delay counter is busy (See also description for Switch S1 in section "Jumpers and Switches"), or
- a VME-commanded veto signal is generated, or
- an external veto signal is generated (spare board only).
BIP-OR (orange) is lit whenever any of the TDCs in the outer huts is in the busy-in-progress (BIP) state.
Fifo Busy (red) monitors the Fifo (V533) busy state.
STRG (green) flashes briefly when a Struck Stop Trigger is generated. It should flash synchronously with the Trigger and FTRG LED if neither veto condition occurs.
FTRG (yellow) flashes briefly when a TDC Common Stop Trigger is generated.
FSCC Resets (4 * red): One LED for each of the outer hut's FSCCs. They flash briefly whenever the FSCCs are fully reset/re-initialized through a VME command. Simultaneously, a warning beeper will be heard as well.
End-of-BIP Trigger (orange) flashes briefly when the end of a TDC BIP signal is detected.

Under normal run conditions, all of the above LEDs - except the 4 FSCC Reset and the Fifo Busy LEDs - should flash synchronously with incoming global triggers.

Schematics and PCB layout

The schematics were edited with ORCAD STD V4 on a 486 PC.

page 1 (gif or postscript): root page,
page 2 (gif or postscript): VME-bus supply and control (Resetter functions),
page 3 (gif or postscript): BIP I/O and fifo flags,
page 4 (gif or postscript): LED DISPLAY Box driver,
page 5 (gif or postscript): Trigger delay and veto,
page 6 (gif or postscript): Output drivers.

The 2-layer PCB layout was edited with TANGO PCB V2, also on a 486 PC. Here's the gif or postscript file of the silk print layer.

PLD Source Codes

The source codes for the 4 PLDs (IC positions U4, U19, U20, U21) are written for TANGO PLD, a compiler for JEDEC format used with PAL/EPROM burners.

VFI_ADDR.TDL (U4): VME address decoder.

Addr.	Data	Addr. Modif.	Write	Addr. Sel.	action
A0...15	D0	AM0...5	/WR	/AS	action
0xD100	X	0x29	0	0	send FSCC hut 1 reset pulse
0xD200	X	0x29	0	0	send FSCC hut 2 reset pulse
0xD300	X	0x29	0	0	send FSCC hut 3 reset pulse
0xD400	X	0x29	0	0	send FSCC hut 4 reset pulse
0xD500	1	0x29	0	0	set veto signal
0xD500	0	0x29	0	0	reset veto signal
X	X	X	1	X	(no action)
X	X	X	X	1	(no action)

where X = don't care

VFI_DCNT.TDL (U19): Trigger delay counter, programmable from 0...19520 nsec in 20 nsec steps.
VFI_VETO.TDL (U20): Veto logic for Struck latch trigger and TDC common stop trigger.
VFI_BIP.TDL (U21): BIP signal "OR" and trailing edge detector with trigger generator and veto signal input logic. See also the flow chart (or ps file) for this code.

Performance Test Results

Revison Notes

06/29/96 - Version 2.0: VFI design finalized for etching.
07/12/96 - Version 2.1:
- Change pin 1 of RN5 and RN6 from VCC to VEE. Mistake in schematics.
- Add sockets for selectable termination resitors on R35 (TRG input, NIM) and on R26 (Fifo Busy input, TTL).
08/11/96 - Version 2.2 (Spare board only): Connector added for external veto signal, e.g. via pulser. This made a slight change of the PLD code for U21 ("VFI_BIP.TDL") nessessary as well.

rev. HGB 01/31/97. Any comments to berns@phys.washington.edu are welcome!