SuperKamiokande Outer ("Anti") Detector Hardware Documentation

As with the inner detector, signals collected in the outer detector PMTs are digitized in each of four quadrant electronics huts. When a detector trigger from any source occurs, the data are passed out of the quadrant huts to the central hut for further processing.

The front end digitizing happens in each of four quadrant electronics huts. The PMT cables are fed into these huts. From there, the signals are picked off, digitized and stored. Local HITSUM pulses are formed and sent to the central hut to form an outer detector (OD) trigger signal. The block diagram above illustrates the data flow in a quadrant hut as well as the overall data flow.

An ECL pulse from a QTC is fed to a LeCroy 1877 Time-to-Digital Converter (TDC) where the leading edges and falling edges are recorded. Each TDC module has 96 input channels (1 per PMT), and there are 5 TDC modules per Fastbus crate and 1 Fastbus crate in each electronics hut, making it a total of 4 x 5 x 96 = 1920 TDC channels.

Each TDC channel works as a circular buffer that can store up to 8 QTC pulses (= digitized PMT pulses) with a resolution of 0.5 nsec over a window of up to 32 µsec wide. If more than 8 PMT pulses occur during a TDC window, then only the most recent 8 pulses are recorded and the earlier ones deleted. The window of OD data-taking originally was 32 µsec wide and centered about the global detector trigger time (16 µsec before and 16 µsec after global trigger). In September 1996 the window was shortened to 16 µsec, with 10 µsec before and 6 µsec after the global detector trigger time. This not only reduced the data size of each event, but also reduced the probability of an overflow of the circular TDC buffers (see background info).

All TDC channels are digitized and read out at the same time after a fixed delay (6 µsec) after a global detector trigger. During digitization, which can take 2 to 15 µsec depending on the number of edges in the event, the OD electronics can not record new data (busy-in-progress dead time), but after read-out the channels are free to take new data. If a global trigger signal is received during OD dead time, a flag bit is introduced into the data stream to record this condition.

The TDC signals are read by a Fastbus Smart Crate Controller (FSCC) which sends the data to the central hut via a connection though a 32-bit RS485 data cable. In the central hut, the data is passed through a DC2/DM115 slave CPU in the OD-DAQ VME crate and stored in a large VME dual-port memory buffer (DPM). One DC2/DM115 module and 2 DPM modules are used for each quadrant TDC data. The OD-DAQ VME crate is controlled by an online CPU, a Sparc20 workstation, via a Bit3 VME-SBus adapter interface.

The online CPU processes the OD data via an OD-DAQ online software set. First, a "collector" process reads out the PMT data from the DPM modules, along with local time stamps from a 50 MHz Local Time Clock counter as well as accurate UTC time from a Global Positioning System (GPS) receiver set. The detector event number and other status bits are also folded in. Then, a "sorter" process merges the quadrant data event by event, adds the time stamps and other event info and re-arranges the data to a new output format for the SK data banks.

Finally, the completed outer detector event data are passed with the "sender" process off to the eventbuilder program running on the online host CPU in the control room via a FDDI connection, from where they are merged with inner detector event data to form a completed full detector event.

Recently added:  
Summer 2003: A Rubidium Frequency Standard (SRS PRS10) was installed in the summer 2003 as a highly accurate 10 MHz source for the Local Time Clock module, where a 1:5 PLL multiplier makes it to high-precision 50 MHz clock signal (replacing the previous standard 50 MHz oscillator). The PRS10 is synchronized with the 1PPS time-sync signal from the backup GPS receiver.
Summer 2004: Uninterruptible Power Supplies (UPS) were installed in the summer 2004 in all 5 electronics huts to provide 120 VAC power failure protection to all OD-DAQ electronics and battery backup time up to 30 minutes during power outages.

Important stuff about the OD-DAQ

• Help! Guide for Super-K Outer Detector Troubles.
• Online manuals for SK shift workers.
• Rules of Engagement for Work at the OD-DAQ.
• NEW! OD-DAQ spare hardware items on site at SK (12/29/2004)

More OD hardware documentation links

• Description of the Anti-Detector [L.Wai 4/17/96]
• OD-DAQ custom electronics documentation [H.Berns]
  ( mirror copy at www-sk.icrr.u-tokyo.ac.jp / Japan).
  • Revision History Memo for OD DAQ custom electronics boards made at UWa.
  • Cabling diagrams: Fastbus crate, VME crate, outer hut interconnections, table of OD-DAQ cables.
  • Inventory of UW SK items: sorted by tag number or location.
• Test Stand for the OD-DAQ [H.Berns 8/30/96].
• Outer Detector High Voltage [Boston U., 3/30/1998]
• Super-K Outer Detector TDC Front-End [E.Kearns].
• User Manual for the Fastbus to VME dual port memory subsystem [M.Chen / J.Goodman, 3/20/96]
• FSCC Data Taking Program Package User Manual [M.Chen, J.Goodman, 12/03/96].

• A list of IP addresses for ethernet nodes used by the OD DAQ system.
• Hyperlinks to data sheets of purchased electronics modules for the OD-DAQ.